Design and analysis of an interleaved step-up DC–DC converter with enhanced characteristics

In this paper, an interleaved DC–DC step-up converter with improved characteristics based on a voltage multiplier rectifier is presented. The proposed converter is presented and analyzed for two different operating duty regions including operating region 1 (0 < D ≤ 0.5), and operating region 2 (0.5 ≤ D < 1). This converter can be used in various applications such as energy storage, electric vehicles, and renewable energy systems. This converter is composed of two stages: an interleaved boost stage and a voltage multiplier rectifier stage, which collectively forms its general structure. The interleaved boost stage is a type of two-phase boost converter that transforms the input DC voltage into a high-frequency AC square waveform. This waveform can be readily filtered using smaller capacitors. The square-shaped voltage waveform from the interleaved boost stage is rectified and converted to a high DC voltage by the Voltage Multiplier Rectifier (VMR) stage. The operating regions, the evaluation of the steady-state condition, the voltage gain of the proposed converter's parasitic and ideal models as well as its losses and efficiency analysis have been evaluated. The proposed converter has an efficiency of 97% at the output power of 150 W. The proposed converter is simulated to convert a voltage of 25–159.5 V and to validate the mathematical relationships and simulation results, a laboratory prototype has been developed. The simulation and experimental results show the precision of the performance of the proposed interleaved boost converter.

The interleaved technique is an internal connection of multiple switching cells that increases the effective pulse frequency by synchronizing several smaller sources and operating them with a suitable phase shift.In medium/high power applications, the interleaved structure can be used to reduce input current ripple, enhance dynamic response, reduce magnetic component sizes, and improve thermal distribution.The interleaved structure decreases input current ripple and increases converter ripple frequency without increasing switching losses or switching device stresses.Therefore, it can reduce the need for filtering and energy storage, thereby significantly improving the power conversion density without compromising the efficiency of the converter.The popularity of interleaved boost DC-DC converters in applications such as energy storage 12 , electric vehicles 13 , and renewable energy systems 14 can be attributed to these advantages.
Various structures have been proposed for interleaved converters.A DC-DC converter utilizing a modified triple-boosting architecture (MTB) interleaved with modified switched inductor capacitors (MSIC) is presented in 15 to attain high voltage gain in photovoltaic applications.A large number of devices and a relatively high switching frequency result in high losses, which are the problems with this structure.An n-phase Interleaved Complementary Current-fed Topology (n-phase ICCFT) with two pulse-width-modulation (PWM) schemes is introduced in 16 to implement the interleaving of the n-phases.This converter has three power switches, which results in a considerable switching loss for this structure and its voltage gain is not a value corresponding to the structure containing three power switches.An interleaved step-up DC-DC converter for high-voltage applications based on a quasi-Z-source is discussed in 17 .All power devices in this converter employ hard switching, which is unsuitable for increasing the switching frequency and reducing switching losses.In 18 , another type of multiphase interleaved step-up converter with soft switching and using an additional resonant circuit is presented.This converter works at a specific frequency which results in low power density.Also, high voltage gain is not properly met in high-duty cycles.The interleaved multilevel boost converter is described in 19 for highvoltage DC microgrid applications.As a result of the increased number of components and voltage gain achieved through the use of multiple stages in this converter, intricate power and control circuits have been developed.In 20 , an interleaved structure along with the multiplier cell is introduced to boost the voltage gain but, because there are so many components in the converter, its efficiency is not impressive.The interleaved boost converter presented in 21 can operate in different regions with different duty cycle values.However, the maximum voltage gain is limited and does not work properly at high powers.In 22 , a symmetrical three-winding coupled inductor (TW-CI) based interleaved step-up converter is introduced.The main issue related to leakage inductance is the occurrence of voltage spikes in the MOSFET switch, leading to considerable power loss and potentially damaging the power switch.An interleaved Luo converter, which combines the advantages of both switched capacitors and interleaved topologies, is utilized in 23 .Also, an Interleaved High-Gain Modified SEPIC (IHGM-SEPIC) DC-DC converter has been presented in 24 for PV applications.In both of these structures, the number of elements used, particularly in 24 , is crucial because it impacts the volume and efficiency of the converter.
The converter's capability for high voltage and high power applications is increased when voltage multipliers (VM) are used in interleaved converters [25][26][27][28][29][30][31][32] .An interleaved step-up converter with a bi-fold Dickson voltage multiplier is reported in 25 and can be used to link medium-voltage distribution buses with low-voltage renewable energy sources.To obtain high voltage gain, this converter employs a switched capacitor technique.Large instantaneous currents passing through the capacitors cause additional power losses, electromagnetic noises, and switch current stress, which is the fundamental drawback of converters based on switched capacitors.Also, the limited range of duty cycle values and a large number of elements are limitations of this structure.The converter described in 26 has a modified Dickson Charge Pump Voltage Multiplier on the output side and a two-phase interleaved step-up converter on the input side which leads to reduced magnetic storage requirements and smoother input current.To rectify or regulate the output voltage, the converter requires an LC filter or output diode.Also, this converter has lower efficiency.This converter needs a capacitor with a high nominal voltage at the output and does not offer a way to lessen the voltage stress on the diode.An interleaved DC-DC step-up converter with an input-parallel output series is introduced in 27 .This converter has two duty regions with different input current ripples and the same voltage gain.However, it has a reverse polarity output.Only in high-duty cycles, this converter can produce a high voltage gain; in lower-duty cycles, the voltage gain is significantly decreased.
An interleaved boost converter with a fixed frequency sliding mode control strategy is provided in 28 to guarantee the system's steady operation.Relatively low voltage gain and complexity in controller design are disadvantages of this converter.In addition, it requires additional current sensors, which increases the hardware cost as a result.In 29 , a tri-state interleaved boost converter is presented.This converter uses a diode and an extra switch to provide a freewheeling time, which keeps the output capacitor's charging time fixed.The dynamic response is enhanced by the tri-state interleaved converter, but the circuit has the same gain as a traditional boost converter and requires more complex control.A multi-input step-up DC-DC converter that is based on the Cockcroft-Walton (CW) multiplier is shown in 30 .In this converter, the current of the input inductors must be controlled by a current balancer.The power density is further limited by the large volume of the required capacitors.Every capacitor in the Cockcroft-Walton voltage multiplier cell experiences the same voltage stress.Increasing the number of the stages of multiplier cells leads to an increase in the output impedance of this cell.Consequently, the converter's efficiency declines.A Greinacher voltage multiplier-based interleaved boost converter is described in 31 .This converter operates properly just for limited duty cycle values.In 32 , an active clamp circuit and a voltage multiplier (VM) are combined for high-voltage applications to introduce and investigate a family of interleaved current-fed step-up DC-DC converters.Because a large number of power devices are used in this converter, the efficiency of the converter is affected by this issue.
In this paper, an interleaved DC-DC step-up converter with improved characteristics such as higher efficiency and relatively higher real voltage gain based on a voltage multiplier rectifier is presented.The power switches experience significantly less voltage stress compared to the output voltage.To reduce conduction losses, power

Proposed converter and operation principles
In this part, the steady-state analysis and operation principles of the proposed converter are explained.The proposed converter is shown in Fig. 1.To analyze the converter, the elements are thought to be ideal, and the capacitor's values are thought to be large enough to overlook voltage ripple.An interleaved step-up stage and a voltage multiplier rectifier (VMR) make up the general structure of the proposed converter.The proposed converter includes two power MOSFETs S 1 , S 2 , two inductors L 1 , L 2 , three capacitors C 1 , C 2 , C 3 , and three diodes D 1 , D 2 , D 3 .In the continuous conduction mode (CCM), the proposed converter has been analyzed.A switching logic has been developed for the operation of the proposed converter in two operating regions including operating region 1 (0 < D ≤ 0.5) and operating region 2 (0.5 ≤ D < 1) which leads to different voltage gains.D is the proposed converter's duty cycle, or the ON time of switches to the switching period.The following subsections provide a comprehensive analysis of the converter's mathematical modeling.
Operating Region 1 (0 < D ≤ 0.5) Figure 2 displays the fundamental operating waveforms of the proposed converter for region 1 (0 < D ≤ 0.5).In this region, S 1 and S 2 are switched in a complementary manner.The proposed converter includes two switching modes (mode 1 and mode 2) during the switching period (T S ), as shown in Fig. 2.

Mode 1 (S 1 off and S 2 on)
The equivalent circuit of the proposed converter when S 1 is off and S 2 is on is shown in Fig. 3a.In this mode, diodes D 1 and D 2 are forward-biased and diode D 3 is reverse-biased.Inductor L 1 discharges its energy into capacitors C 1 and C 2 .Therefore, its current slope is negative according to Fig. 2. The inductor L 2 is charged through the input voltage V in .In Fig. 2, the current slope of inductor L 2 is positive.The energy stored in the capacitor C 3 is discharged into the output load R. The resulting equations in mode 1 are according to relations (1), (2).
(1) The equivalent circuit of the proposed converter when S 1 is on and S 2 is off is shown in Fig. 3b.In this mode, diodes D 1 and D 2 are reverse biased and diode D 3 is forward biased.The stored energy is delivered to the output load and output capacitor C 3 by inductor L 2 and capacitors C 1 and C 2 .Therefore, according to Fig. 2, the current slope of the inductor L 2 and the voltage slope of the capacitors C 1 and C 2 are negative in this mode.The inductor L 1 is charged through the input voltage V in .Also, according to the positive slope of the inductor L 1 's current in Fig. 2, it can be concluded that the inductor L 1 is charging.The resulting equations in mode 2 are according to relations (3), (4).

Operating region 2 (0.5 ≤ D < 1)
The essential operating waveforms of the proposed converter for region 2 (0.5 ≤ D < 1) are shown in Fig. 4. In this region, there is a 180 ° phase difference between S 1 and S 2 .From Fig. 4, it can be seen that the proposed converter has three switching modes (mode 1, mode 2, and mode 3) in the switching period (T S ).

Mode 1 (S 1 on and S 2 on)
The equivalent circuit of the proposed converter when S 1 and S 2 are on is shown in Fig. 5a.In this mode, the inductors are charged through the input source, and the diodes are reverse-biased.The energy stored in the capacitor C 3 is discharged into the output load R. Capacitors C 1 , C 2 , and C 3 is neither charged nor discharged.As seen in Fig. 4, the inductors' current slope is positive, indicating that they are charged in this mode.Also, the voltage slope of capacitors C 1 , C 2 , and C 3 remains constant.The resulting equations in mode 1 are in the form of relations ( 5), (6).

Mode 2 (S 1 off and S 2 on)
The equivalent circuit of the proposed converter when S 1 is off and S 2 is on is shown in Fig. 5b.In this mode, diodes D 1 and D 2 are forward-biased biased, and diode D 3 is reverse-biased.L 1 discharges its energy into capacitors C 1 and C 2 .Therefore, its current slope is negative according to Fig. 4. The inductor L 2 is charged through the input voltage V in .In Fig. 4, the current slope of inductor L 2 is positive.The energy stored in the capacitor C 3 is discharged into the output load R. The resulting equations in mode 1 are according to relations (7), (8).

Mode 3 (S 1 on and S 2 off)
The equivalent circuit of the proposed converter when S 1 is on and S 2 is off is shown in Fig. 5c.In this mode, diodes D 1 and D 2 are reverse biased and diode D 3 is forward biased.The stored energy is delivered to the output load and output capacitor C 3 by inductor L 2 and capacitors C 1 and C 2 .Therefore, according to Fig. 4, the current slope of the inductor L 2 and the voltage slope of the capacitors C 1 and C 2 are negative in this mode.The inductor L 1 is charged through the input voltage V in .Also, according to the positive slope of the inductor L 1 's current in Fig. 4, it can be concluded that the inductor L 1 is charging.The resulting equations in mode 3 are according to relations ( 9), (10).

Steady-state analysis
This part includes a detailed analysis of the proposed converter's ideal and real voltage gains, parameters design, voltage stress on the diodes and switches, and, lastly, the calculations of losses and efficiency in the continuous conduction mode (CCM).Since the proposed converter has two types of switching logic for duty cycles less than and greater than 0.5, the ideal and real voltage gain, as well as the design of the parameters for the two operating regions, are presented.

Ideal voltage gain in operating region 1 (0 < D ≤ 0.5)
By applying the volt-second balance principle on the inductors in a switching period in the operation region 1 according to Eqs. ( 11) and ( 12), the voltage of the capacitors is obtained according to Eq. ( 13), which can be used to achieve the ideal voltage gain.www.nature.com/scientificreports/Therefore, by substituting Eq. ( 13) into Eqs.( 11) and ( 12), the ideal voltage gain of the proposed converter is obtained as follows.www.nature.com/scientificreports/As it is known, the voltage of capacitor C 1 is equal to the voltage of capacitor C 2 .It is also worth mentioning that the ideal voltage gain calculated for the duty cycle is valid in the range (0 < D ≤ 0.5).

Ideal voltage gain in operating region 2 (0.5 ≤ D < 1)
By applying the volt-second balance principle on the inductors in a switching period in the operation region 2 according to Eqs. ( 15) and ( 16), the voltage of the capacitors is obtained according to Eq. ( 17), and by using these equations, the ideal voltage gain of the proposed converter can be obtained.Therefore, by substituting Eq. ( 17) into Eqs.( 15) and ( 16), the ideal voltage gain of the proposed converter is obtained as follows.
As it is known, the voltage of capacitor C 1 is equal to the voltage of capacitor C 2 .It is also worth mentioning that the ideal voltage gain calculated for the duty cycle is valid in the range (0.5 ≤ D < 1).

Real voltage gain
This section presents an analysis of the impact of parasitic elements on the output voltage and efficiency.Figure 6 illustrates the proposed converter circuit with parasitic elements.The inductors' equivalent series resistance (ESR) includes r L1 and r L2 .r S1 , r S2 represent the switches' on-state resistances, while r D1 , r D2 and r D3 are the internal resistances of the diodes and V D1 , V D2 and V D3 are their forward bias voltage drops.r C1 , r C2 and r C3 are the equivalent series resistance (ESR) of capacitors C 1 , C 2 and C 3 .
The operation principles of the proposed converter in real conditions are similar to the operation principles in the ideal state, and the parasitic elements are also considered in the equivalent circuit and the governing equations of the circuit.Similar to ideal voltage gain calculations, by applying the volt-second balance principle to the inductors and taking into account the parasitic parameters, the real voltage gain of the proposed converter is calculated in operating region 1 (0 < D ≤ 0.5) according to Eq. ( 19) and in operating region 2 (0.5 ≤ D < 1) according to Eq. ( 20). ( 15) www.nature.com/scientificreports/ In the following, the process of parameter design for the proposed converter has been examined.The parameter design has been checked once for the operating region 1, which has a duty cycle of less than 0.5, and repeated for the operating region 2, which has a duty cycle of more than 0.5.

Inductor selection
When the switches S 1 and S 2 are on, the inductors L 1 and L 2 have a positive current slope, and the voltage of capacitors and relations (1) and ( 3) can be used to determine the current ripple of inductors, which yields relations ( 21) and (22).
Hence, the values of inductors L 1 and L 2 operating under continuous conduction mode (CCM) are obtained according to relations (23) and (24).
The average current passing through inductors L 1 and L 2 is as follows: The peak passing current of inductors L 1 and L 2 can be calculated according to relations (27) and (28).

Active switches selection
The voltage stress across switches S 1 and S 2 can be obtained using the relations (31) and (32).
The average current passing through switches S 1 and S 2 is as follows: The peak current passing through switches S 1 and S 2 is obtained according to (35).
The root mean square (RMS) values of the switch's current can be obtained using the relations ( 31) and (32).

Diode selection
The voltage stress across the diodes in the proposed structure can be calculated using the following equation: The average current passing through all the diodes is as follows: The RMS current passing through diodes D 1 , D 2 , and D 3 can be expressed by relation (40).

Capacitor selection
An important factor in choosing a capacitor is its permissible voltage ripple.Using Eq. ( 2) and the values of the average current of the inductor, the voltage ripple of the capacitors can be obtained as follows.
Allowable voltage ripple of capacitors is considered to achieve proper performance and low power loss.Using Eq. (41), the capacitor capacity can be derived as follows: (30)

Inductor selection
In this operating region, considering that the converter has three operating modes, depending on which of the operating modes is selected and according to the equations governing the considered mode and voltage of capacitors, the current ripple of inductors can be expressed according to relations (43) and (44).
Hence, the values of inductors L 1 and L 2 operating under continuous conduction mode (CCM) are obtained according to relations (45) and (46).
The average current through the inductors L 1 and L 2 in operation region 2 is as follows: The peak current of inductors L 1 and L 2 can be calculated according to the relations (49) and (50).
The RMS current of inductors L 1 and L 2 can be expressed by relations (51) and (52).

Active switches selection
The voltage stress of switches S 1 and S 2 can be obtained using the following relation: The average current passing through switches S 1 and S 2 can be expressed according to Eq. ( 54) and their peak current can be expressed according to Eq. (55).

Diode selection
The voltage stress of the diodes can be obtained using the Eq.(56) below.
(43 www.nature.com/scientificreports/ The average current passing through diodes can be expressed according to Eq. ( 57) and the RMS current passing through diodes D 1 , D 2 , and D 3 can be expressed by Eq. (58).

Capacitor selection
An important factor in choosing a capacitor is its permissible voltage ripple.Equation (59) can be used to determine the voltage ripple of the capacitors based on the average current values of the inductors and the equations governing each of the three considered modes.Equation (60) can be used to calculate the capacitor capacity of the proposed converter for operating region 2.

Analysis of power loss and efficiency
As previously mentioned, parasitic resistances cause power losses and affect the performance and efficiency of converters.Different power losses in a converter must be considered and calculated.The power loss of a converter includes switch losses, which include conduction and switching losses, diode losses, inductor losses, and capacitor losses.The total power loss is obtained by summing all the described losses.In the following, each of the above losses is examined and how to calculate them is explained.
The switch losses are classified into two groups conductive and switching losses, which are calculated as relations ( 61) and (62), respectively.where V DS is the switch's standing voltage and I S,avg is the average current flowing through the switch.The switch's rise and fall times are described as (t r , t f ).The Switching frequency is f s and finally I S,rms indicate the effective current passing through the switch.The power losses of diodes can be calculated from the following equation, where r D is the diode conduction resistance, I D,rms is the effective current that flows through the diode, V D is the diode's forward voltage drop, and I D,avg is the average current that flows through the diode.
Similarly, relations (64) and (65) can be used to calculate the power losses of inductors and capacitors, respectively.
Table 1.The parasitic values of the proposed converter for loss analysis and real gain factor.

Parasitic parameter Values
Switches' on-state resistance r DS = 0.04 Ω Diodes' on-state resistance r d = 0.17 With all of the aforementioned losses taken into account, relations (66) and (67) yield the total power losses and converter efficiency, respectively.
To analyze the losses and obtain the efficiency of the proposed converter, the parasitic values are considered according to Table 1. Figure 7 shows the efficiency and power loss analysis of the proposed converter in different duty cycles.The efficiency according to the duty cycle at a constant power of 200 W for input voltages of 25 V and 40 V is represented in Fig. 7a.According to this figure, for a higher input voltage and at a given power, the current passing through the elements is lower, and better efficiency is obtained.According to this figure, the efficiency of the proposed converter in a wide range of duty cycles and different input voltages is suitable and acceptable and provides values of 93%-98%.Furthermore, Fig. 7b displays the power loss distribution of the proposed converter at D = 0.55 and V in = 25 V.The power loss distribution is determined by the proposed converter in MATLAB software using equations described in relations (61)-(67) for an output power of 200 W.According to Eq. ( 61), the losses caused by switches are equal to 2.2934 W. Diode losses using Eq. ( 63) are obtained at 1.658 W. The losses resulting from inductors and capacitors are 2.3915 W and 0.07657 W, respectively, (65)    64) and (65).Finally, the converter efficiency is 96.89% and the total losses, including the sum of the aforementioned losses, are 6.419 W.

Comparison of interleaved converters
A comparison with some similar converters described in 20,21,23 , and 26 under the same conditions has been conducted to validate the proposed converter.and for the duty cycle of 0.5 ≤ D < 1. Table 2 presents the results of the comparison of these converters with the proposed converter according to the number of elements, voltage gain, maximum voltage stress of switches, maximum voltage stress of diodes, efficiency, continuous input current, and common ground.According to the total number of elements, the conditions for the structures under comparison are close to each other and the total number of elements in the structures of 21,23 , and 26 is 8, 11, and converter in [21], [26]  converter in [23]  converter in [20], proposed converter  converter in [20], [21], [23], [26], proposed converter  [20], D1 in [21], [26], proposed converter D2 in [21], [23]   Figure 10.Voltage stress on the diodes according to the duty cycle (D).9 elements, respectively, and it is equal to 10 in the proposed converter and other structure.The relationship of voltage gain (M) according to duty cycle (D) for different structures is presented in Table 2 and Fig. 8 shows the structures' voltage gain.According to this figure, the proposed converter's voltage gain for the same duty cycle is better than the structures under comparison.Also, the voltage gain of the proposed converter is even better than the structure 23 , which has more elements.Table 2 presents the maximum voltage stress relationship on the switches according to the duty cycle (D), and Fig. 9 illustrates the maximum voltage stress of the switches in the comparison structures.This figure illustrates that, although the proposed converter has a higher ideal voltage gain, the voltage stress on the switches is consistent across all compared structures, and they are all positioned similarly.In Fig. 10, the maximum voltage stress on the diodes is also displayed according to the duty cycle (D).Considering that the voltage gain of the proposed converter is greater than that of other structures, it is natural that the maximum voltage stress of the diodes in the proposed converter is higher than some comparative structures.In addition, according to Fig. 10, in the structure of 20,26 , and diode D 1 of 21 , the voltage stress governing the diodes is the same as the proposed converter.In Table 2, the efficiency of the compared and proposed structures is presented.It is worth noting that the proposed converter demonstrates higher efficiency compared to the other structures.While the structure 23 is reported to have an efficiency of 98.6% at a power of 900 W, this value is reported without considering the same conditions as the proposed converter.Based on Fig. 12, when the same conditions as those in Table 1 for the proposed converter are applied to this structure within the same power range, it is evident that the proposed converter outperforms it and exhibits superior efficiency.
The real voltage gain of the proposed converter and the structure 20 are plotted in Fig. 11 for the same parasitic values for both converters and according to the duty cycle (D).Although the number of components, ideal voltage gain, voltage stress of the switch and diode, and other parameters of the structure 20 are identical to those of the proposed structure, in practical conditions and terms of parasitic resistances, its real voltage gain is lower than the proposed converter for duty cycle in the range of 0.8 ≤ D < 0.95.This shows the relative superiority of the proposed converter over this structure.Also, the polarity of the output voltage in this structure is reversed, which causes a limitation in its performance, which does not exist in the proposed converter.
Figure 12 shows the efficiency of the proposed converter and structures 20 and 23 considering the same parasitic values.According to this figure, the efficiency of the proposed converter is better than these two structures.The structure 23 has more elements with a lower voltage gain factor, which causes higher losses and affects the efficiency of this converter.Finally, the proposed converter can be considered a better option compared to the mentioned references, considering that it has relative superiority in comparison.converter in [20]  proposed converter efficiency of proposed converter efficiency of converter in [23]  efficiency of converter in [20]   Figure 12.Efficiency of the proposed converter and structures 20 and 23 .

Simulation results
The MATLAB software simulations have been done with the parameters listed in Table 3 to verify the proposed converter's operation.The results of the simulation are displayed in Figs. 13, 14, 15 and 16.It is worth noting that to simulate the real conditions, the simulation has been done considering the parasitic parameters and for the operating region 2 (0.5 ≤ D < 1).The values of the parasitic parameters have been applied in the simulation according to the information in Table 1.The gate signals of switches S 1 and S 2 are shown in Fig. 13a, which work with a duty cycle of 0.55 and are switched at a 180 • phase difference from each other.According to Fig. 13b, the output voltage is equal to 159.5 V. Considering the ideal and real voltage gain of the proposed converter in Eqs.(18) and ( 20) respectively, the output voltage of the converter is 166 V in the ideal state and 159.88 V in the real state, which confirms the results of the simulation.It should be noted that if a switch and diodes with lower on-state resistance are used, the difference between the ideal and real conditions is reduced.Figure 13c shows the output current of the converter; the average value of the output current is about 0.95 A. The voltage of capacitors C 1 and C 2 is shown in Fig. 13d, the  www.nature.com/scientificreports/average of which is 53.04 V.According to Eq. ( 17), the voltage of capacitors C 1 and C 2 is equal to 55.55 V, which is very close to the theoretical value.Figure 14 shows the voltages and currents passing through diodes D 1 , D 2 , and D 3 .Because diodes D 1 and D 2 turn on and off in the same modes, they have the same voltage and current waveforms.Also, according to Eq. ( 56), all three diodes experience the same voltage.In Fig. 14a and c, this value is 108.5 V, which is close to the theoretical value of 111.1 V.In Fig. 14b and d the current of the diodes is shown, according to the Eq.(57), its average value is almost equal to the output current and about 0.95 A.
Figure 15 shows the voltage and current of switches S 1 and S 2 , respectively.The voltage stress of the switches is 54.51 V, which is consistent with Eq. (53).Also, the voltage stress of the switches is much lower than the output voltage and about one-third of the output voltage, which is a good advantage for the converter.The current passing through switches S 1 and S 2 are shown in Fig. 15b and d, respectively.The peak current passing through the switches is 6.871 A.
In Fig. 16a the input voltage and current can be seen.As mentioned in Table 3, the input voltage is 25 V.The average value of the input current is equal to 6.728 A, which can be seen in Fig. 16b.Also, the average current of inductors L 1 and L 2 are 4.378 A and 2.350 A, respectively.It is worth mentioning that the input current ripple is less than the current ripple of inductors, which is the result of using the interleaved technique in the proposed converter.

Experimental results
A laboratory prototype designed to verify the proposed converter's specifications, theoretical calculations, and simulation results is depicted in Fig. 17 The gate signal of the switches is shown in Fig. 18a.As mentioned before, these signals have a phase difference of 180 • .Figure 18b shows the output voltage and current.According to the simulation results, the output voltage at a duty cycle of 55% and an input voltage of 25 V is approximately 159 V. Also, the average value of the output current is 0.94 A, which confirms the results of the simulation.The voltage of capacitors C 1 and C 2 is shown in Fig. 18c.Theoretically, the voltage of capacitors is calculated as 55.55 V according to Eq. ( 17), which is nearly the same as the experimental result.It is worth noting that the difference between simulation and experimental values is due to losses in laboratory conditions.
According to Fig. 19a, the voltage and average current of diodes D 1 and D 2 are equal to 111 V and 0.94 A, respectively.Also, according to Fig. 19b, the voltage across diode D 3 is equal to 108 V, and the average current passing through diode D 3 is about 0.94 A, and these values are consistent with the simulation results and theoretical calculations.Also, according to Fig. 19, the maximum current passing through the diodes is 2 A which    is consistent with the simulation results.Figures 20a and b show the voltage and current stress on the switches.According to this figure, the voltage stress on the switches is about 54 V and the peak current passing through the switches is about 6.8 A, which does not contradict the results of the simulation and the resulting relationships.Figure 21 also shows the input voltage and current and the current of the inductors, which according to Fig. 16, the experimental results and the simulation results match.

Conclusion
In this paper, an interleaved DC-DC step-up converter with improved voltage gain based on a voltage multiplier rectifier is presented.The proposed interleaved DC-DC step-up converter has two operating regions (0 < D ≤ 0.5, 0.5 ≤ D < 1).The configuration of the proposed converter has been investigated and its operating modes have been carried out under continuous conduction mode (CCM).Ideal and real voltage gain have been calculated and compared with similar structures.The proposed converter has been compared to similar converters in terms of component count, voltage gain, and voltage stress on switches and diodes.The results that have been presented indicate that, for the same duty cycle, the voltage gain of the proposed converter is higher and, in some situations, equal to that of similar converters.The voltage stress of the switches is much lower than the output voltage.
Taking into account the proposed converter's continuous input current and easy control circuit, the proposed converter seems like a good choice for DC microgrid systems.The proposed converter's input current ripple is lower than the current ripple of the inductors due to the use of the interleaved technique, which reduces the need for filters.By taking into account the parasitic parameters, the efficiency, and real voltage gain have been measured accurately, and at 150 W power, the efficiency is 97%.The comparisons show that the proposed converter has suitable conditions in terms of voltage gain in both ideal and parasitic conditions.Simulation analysis is provided by MATLAB software to validate the mathematical calculations.Also, the experimental results of the laboratory prototype show full agreement with the simulation results.

Figure 2 .
Figure 2. Essential operating waveforms of the proposed converter for 0 < D ≤ 0.5.

Figure 3 .
Figure 3. Equivalent circuit of different switching modes of the proposed converter in operating region 1: (a) S 1 off and S 2 on (b) S 1 on and S 2 off.

Figure 5 .
Figure 5. Equivalent circuit of different switching modes of the proposed converter in operating region 2: (a) S 1 on and S 2 on (b) S 1 off and S 2 on (c) S 1 on and S 2 off.

Figure 6 .
Figure 6.Effect of parasitic elements in the proposed converter's structure.

Figure 7 .
Figure 7. Analysis of efficiency and power losses of the proposed converter.(a) Efficiency according to duty cycle at constant power of 200 W and different input voltage.(b) Power loss distribution.

Figure 8 .
Figure 8. Voltage gain according to the duty cycle (D).

Figure 9 .
Figure 9. Switch's voltage stress according to the duty cycle (D).

Figure 11 .
Figure 11.The parasitic voltage gain of the proposed converter and structure 20 .
. The parameters in Table3have been used to set up the laboratory sample along with the IRFP260N MOSFET and MBR20B200 diode.The results and waveforms of the proposed converter in continuous conduction mode (CCM) and at a switching frequency of 50 kHz with D = 0.55 are shown in Figs.18, 19, 20 and 21.

Figure 16 .
Figure 16.Results of the simulation: (a) input voltage and current, (b) input current, current of inductor L 1 and current of inductor L 2 .

Figure 19 .
Figure 19.Experimental results: (a) voltage and current of diodes D 1 and D 2 , (b) voltage and current of diode D 3 .

Figure 20 .
Figure 20.Experimental results: (a) voltage and current of switch S 1 , (b) voltage and current of switch S 2 .

Figure 21 .
Figure 21.Experimental results: (a) current of inductor L 1 , (b) current of inductor L 2 , (c) input voltage and current.
Proposed converter.

Table 2 .
Comparison of the characteristics of the proposed converter and some references.

Table 3 .
Parameters of the proposed converter.